mcm67b618a 1 motorola fast sram 64k x 18 bit burstram synchronous fast static ram with burst counter and selftimed write the mcm67b618a is a 1,179,648 bit synchronous fast static random access memory designed to provide a burstable, highperformance, secondary cache for the i486 ? and pentium ? microprocessors. it is organized as 65,536 words of 18 bits. the device integrates input registers, a 2bit counter, high speed sram, and high drive capability outputs onto a single monolithic circuit for re- duced parts count implementation of cache data ram applications. synchro- nous design allows precise cycle control with the use of an external clock (k). bicmos circuitry reduces the overall power consumption of the integrated func- tions for greater reliability. addresses (a0 a15), data inputs (d0 d17), and all control signals except output enable (g ) are clock (k) controlled through positiveedge triggered noninverting registers. bursts can be initiated with either address status processor (adsp ) or address status cache controller (adsc ) input pins. subsequent burst addresses can be generated internally by the mcm67b618a (burst sequence imitates that of the i486 and pentium) and controlled by the burst address advance (adv ) input pin. the following pages provide more de- tailed information on burst controls. write cycles are internally selftimed and are initiated by the rising edge of the clock (k) input. this feature eliminates complex offchip write pulse generation and provides increased flexibility for incoming signals. dual write enables (lw and uw ) are provided to allow individually write- able bytes. lw controls dq0 dq8 (the lower bits), while uw controls dq9 dq17 (the upper bits). this device is ideally suited for systems that require wide data bus widths and cache memory. see figure 2 for applications information. ? single 5 v 5% power supply ? fast access times: 9/10/12 ns max ? byte writeable via dual write enables ? internal input registers (address, data, control) ? internally selftimed write cycle ? adsp , adsc, and adv burst control pins ? asynchronous output enable controlled threestate outputs ? common data inputs and data outputs ? 3.3 v i/o compatible ? high board density 52lead plcc package i486 and pentium are trademarks of intel corp. 10 9 8 dq9 v cc dq8 12 11 15 14 13 17 16 20 19 18 37 38 34 35 36 42 43 39 40 41 45 46 44 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 54 32 1525150494847 dq6 dq7 v ss dq4 dq5 dq2 dq3 v ss v cc dq0 dq1 v cc v ss v ss v cc dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 a6 a7 e uw k a8 a9 a10 lw g a15 a4 a3 a2 a1 a13 a14 a12 a11 v ss a5 a0 v cc adv adsc adsp all power supply and ground pins must be connected for proper operation of the device. pin names a0 a15 address inputs . . . . . . . . . . . . . . . . k clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . adv burst address advance . . . . . . . . . . . . lw lower byte write enable . . . . . . . . . . . . uw upper byte write enable . . . . . . . . . . . . adsc controller address status . . . . . . . . . adsp processor address status . . . . . . . . . e chip enable . . . . . . . . . . . . . . . . . . . . . . . . . g output enable . . . . . . . . . . . . . . . . . . . . . . dq0 dq17 data input/output . . . . . . . . . . v cc + 5 v power supply . . . . . . . . . . . . . . . . v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . nc no connection . . . . . . . . . . . . . . . . . . . . . pin assignments order this document by mcm67b618a/d semiconductor technical data mcm67b618a fn package plastic case 77802 rev 2 11/5/96 ? motorola, inc. 1996 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 2 motorola fast sram block diagram (see note) binary counter dq0 dq8 clr q0 q1 a0 a1 k adsc adsp a0 a15 e g address register write register enable register datain registers output buffer 64k 18 memory array adv burst logic internal address a0 a1 16 9 18 16 2 a2 a15 a1 a0 dq9 dq17 9 9 9 9 9 uw lw note: all registers are positiveedge triggered. the adsc or adsp signals control the duration of the burst and the start of the next burst. when adsp is sampled low, any ongoing burst is interrupted and a read (independent of w and adsc ) is per- formed using the new external address. alternatively, an adsp initiated two cycle write can be performed by asserting adsp and a valid address on the first cycle, then negating both adsp and adsc and asserting lw and/or uw with valid data on the second cycle (see single write cycle in write cycles timing diagram). when adsc is sampled low (and adsp is sampled high), any ongoing burst is interrupted and a read or write (dependent on w ) is performed using the new external address. chip enable (e ) is sampled only when a new base address is loaded. after the first cycle of the burst, adv controls subsequent burst cycles. when adv is sampled low, the internal address is advanced prior to the operation. when adv is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. upon completion of a burst, the address will wrap around to its initial state. see burst sequence table . write refers to either or both byte write enables (lw , uw ). burst sequence table (see note) external address a15 a2 a1 a0 1st burst address a15 a2 a1 a0 2nd burst address a15 a2 a1 a0 3rd burst address a15 a2 a1 a0 note: the burst wraps around to its initial state upon completion. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 3 motorola fast sram synchronous truth table (see notes 1, 2, and 3) e adsp adsc adv uw or lw k address used operation h l x x x lh n/a deselected h x l x x lh n/a deselected l l x x x lh external address read cycle, begin burst l h l x l lh external address write cycle, begin burst l h l x h lh external address read cycle, begin burst x h h l l lh next address write cycle, continue burst x h h l h lh next address read cycle, continue burst x h h h l lh current address write cycle, suspend burst x h h h h lh current address read cycle, suspend burst notes: 1. x means don't care. 2. all inputs except g must meet setup and hold times for the lowtohigh transition of clock (k). 3. wait states are inserted by suspending burst. asynchronous truth table (see notes 1 and 2) operation g i/o status read l data out read h highz write x highz e data in deselected x highz notes: 1. x means don't care. 2. for a write operation following a read operation, g must be high before the input data required setup time and held high through the input data hold time. absolute maximum ratings (voltages referenced to v ss = 0 v) rating symbol value unit power supply voltage v cc 0.5 to + 7.0 v voltage relative to v ss for any pin except v cc v in , v out 0.5 to v cc + 0.5 v output current (per i/o) i out 30 ma power dissipation p d 1.6 w temperature under bias t bias 10 to + 85 c operating temperature t a 0 to +70 c storage temperature t stg 55 to + 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 4 motorola fast sram dc operating conditions and characteristics (v cc = 5.0 v 5%, t a = 0 to + 70 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min max unit supply voltage (operating voltage range) v cc 4.75 5.25 v input high voltage v ih 2.2 v cc + 0.3 ** v input low voltage v il 0.5* 0.8 v *v il (min) = 0.5 v dc; v il (min) = 2.0 v ac (pulse width 20.0 ns) for i 20.0 ma. ** v ih (max) = v cc + 0.3 v dc; v ih (max) = v cc + 2.0 v ac (pulse width 20.0 ns) for i 20.0 ma. dc characteristics and supply currents parameter symbol min max unit input leakage current (all inputs, v in = 0 to v cc ) i lkg(i) e 1.0 m a output leakage current (g = v ih ) i lkg(o) e 1.0 m a ac supply current (g = v ih , e = v il , i out = 0 ma, all inputs = v il or v ih , v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) i cca9 i cca10 i cca12 e 275 265 250 ma ac standby current (e = v ih , i out = 0 ma, all inputs = v il and v ih, v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) i sb1 e 95 ma output low voltage (i ol = + 8.0 ma) v ol e 0.4 v output high voltage (i oh = 4.0 ma) v oh 2.4 3.3 v note: good decoupling of the local power supply should always be used. dc characteristics are guaranteed for all possible i486 and pentium bus cycles. capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 25 c, periodically sampled rather than 100% tested) parameter symbol typ max unit input capacitance (all pins except dq0 dq17) c in 4 5 pf input/output capacitance (dq0 dq17) c i/o 6 8 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 5 motorola fast sram ac operating conditions and characteristics (v cc = 5.0 v 5%, t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 1a unless otherwise noted . . . . . . . . . . . . . read/write cycle timing (see notes 1, 2, 3, and 4) mcm67b618a9 mcm67b618a10 mcm67b618a12 parameter symbol min max min max min max unit notes cycle time t khkh 15 e 16.6 e 20 e ns clock access time t khqv e 9 e 10 e 12 ns 5 output enable to output valid t glqv e 5 e 5 e 6 ns clock high to output active t khqx1 6 e 6 e 6 e ns clock high to output change t khqx2 3 e 3 e 3 e ns output enable to output active t glqx 0 e 0 e 0 e ns output disable to q highz t ghqz e 6 e 7 e 7 ns 6 clock high to q highz t khqz 3 6 3 7 e 7 ns clock high pulse width t khkl 5 e 5 e 6 e ns clock low pulse width t klkh 5 e 5 e 6 e ns setup times: address address status data in write address advance chip enable t avkh t adsvkh t dvkh t wvkh t advvkh t evkh 2.5 e 2.5 e 2.5 e ns 7 hold times: address address status data in write address advance chip enable t khax t khadsx t khdx t khwx t khadvx t khex 0.5 e 0.5 e 0.5 e ns 7 notes: 1. in setup and hold times, w (write) refers to either one or both byte write enables lw and uw . 2. a read cycle is defined by uw and lw high or adsp low for the setup and hold times. a write cycle is defined by lw or uw low and adsp high for the setup and hold times. 3. all read and write cycle timings are referenced from k or g . 4. g is a don't care when uw or lw is sampled low. 5. maximum access times are guaranteed for all possible i486 and pentium external bus cycles. 6. transition is measured 500 mv from steadystate voltage with load of figure 1b. this parameter is sampled rather than 100% tested. at any given voltage and temperature, t khqz max is less than t khqz1 min for a given device and from device to device. 7. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of k whenever adsp or adsc is low, and the chip is selected. all other synchronous inputs must meet the specified setup and hold times for all rising edges of k when the chip is enabled. chip enable must be valid at each rising edge of clock for the device (when adsp or adsc is low) to remain enabled. (a) (b) 5 pf + 5 v output 480 w 255 w output z 0 = 50 w r l = 50 w v l = 1.5 v figure 1. test loads f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 6 motorola fast sram q(a2 + 2) q(a2 + 1) q(a2) q(a2 + 3) q(a2 + 2) q(a2 + 1) q(a2) q(a1) burst read (adv suspends burst) (burst wraps around to its initial state) single read adsc t khqz t khqv t khqx2 t ghqz t glqx t glqv t khqv t khadvx t advvkh t khex t evkh t khwx t wvkh t khadsx t adsvkh t khax t avkh t klkh t khkl t adsvkh t khkh t khadsx data out g e k adsp address lw, uw note: q(a2) represents the first output data from the base address a2; q(a2 + 1) represents the next output data in the burst sequence with a2 as the base address. a1 a2 adv read cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 7 motorola fast sram w is ignored for first cycle when adsp initiates burst new burst write burst write adv suspends burst t khdx t dvkh t khadvx t advvkh t khwx t wvkh adsc starts new burst a3 d(a3 + 2) d(a3 + 1) d(a3) d(a2 + 3) d(a2 + 2) d(a2 + 1) d(a2) d(a2 + 1) t khadsx t adsvkh t khkh t khkl t klkh d(a1) t khadsx t adsvkh t khax t avkh t khex t evkh single write burst read t ghqz k adsp adsc address adv g data in data out a1 a2 e lw, uw write cycles q(an 1) q(an) (with a suspended cycle) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 8 motorola fast sram combination read/write cycle (e low, adsc high) k adsp address lw , uw adv g data in data out read write burst read t khkh t adsvkh t khadsx t khkl t klkh a1 a2 a3 t avkh t khax t wvkh t khwx t advvkh t khadvx t khqv t khqx1 t ghqz t dvkh t khdx t glqx t khqx2 d(a2) q(a1) q(a3) q(a3 + 1) q(a3 + 2) t glqv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 9 motorola fast sram application example 512k byte burstable, secondary cache using four mcm67b618afn9s with a 66 mhz pentium data address clk ads control cache control logic adv adsp k adsc w g data bus address bus mcm67b618afn9 pentium ? clock addr addr data k figure 2 ordering information (order by full part number) mcm 67b618a xx xx motorola memory prefix part number full part numbers e mcm67b618afn9 MCM67B618AFN10 mcm67b618afn12 speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns) package (fn = plcc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mcm67b618a 10 motorola fast sram package dimensions fn package 52lead plcc case 77802 a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim 19.94 19.94 4.20 2.29 0.33 0.66 0.51 0.64 19.05 19.05 1.07 1.07 1.07 e 2 18.04 1.02 20.19 20.19 4.57 2.79 0.48 0.81 e e 19.20 19.20 1.21 1.21 1.42 0.50 10 18.54 e 0.785 0.785 0.165 0.090 0.013 0.026 0.020 0.025 0.750 0.750 0.042 0.042 0.042 e 2 0.710 0.040 0.795 0.795 0.180 0.110 0.019 0.032 e e 0.756 0.756 0.048 0.048 0.056 0.020 10 0.730 e 1.27 bsc 0.050 bsc notes: 1. due to space limitation, case 778-02 shall be represented by a general (smaller) case outline drawing rather than showing all 52 leads. 2. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 3. dim g1, true position to be measured at datum -t-, seating plane. 4. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 5. dimensioning and tolerancing per ansi y14.5m, 1982. 6. controlling dimension: inch. 7. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 8. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). g1 view s -n- -m- -l- c e j g z a r d w d 1 v y brk 52 leads actual (note 1) 52 b u z view d-d h k1 k view s f g1 x 0.007 (0.180) t l m s n s m 0.007 (0.180) t l m s n s m 0.007 (0.180) t l m s n s m 0.007 (0.180) t l m s n s m 0.007 (0.180) t l m s n s m 0.007 (0.180) t l m s n s m 0.010 (0.250) t l m s n s s 0.010 (0.250) t l m s n s s 0.004 (0.100) seating plane -t- (note 1) 52 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 nishi-gotanda, shinagawa-ku, tokyo, japan. 81-3-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system us & c anada only 1-800-774-1848 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. http ://sps.motorola.com /mfax / 852-26629298 home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm67b618a/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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